The present invention relates to a semiconductor memory device, a semiconductor device, and a method for production thereof. More particularly, the present invention relates to a semiconductor memory device, a semiconductor device, and a method for production thereof, the semiconductor having a memory node contact or other contacts for DRAM (dynamic random access memory).
The recent advance in semiconductor devices (such as VLSI) is remarkable. In the last three years, they have decreased in size by 70 percent and increased in the degree of integration in proportion to size reduction. They have achieved higher performance than before.
The ever-increasing degree of integration is exemplified by the MOS-type DRAM in which one memory cell is composed of one switching transistor (metal oxide semiconductor field effect transistor [MOSFET]) and one memory capacitor. This DRAM functions as the process driver in semiconductor devices.
The miniaturization of devices decreases the area of the memory cell and reduces the area of the memory capacitor accordingly.
Despite reduction in its area, the memory capacitor remained unchanged in its storage capacity at 20 to 30 fF per bit over the past generations of DRAM, because a certain amount of storage capacity is necessary to ensure operational margin and effectively protect stored data from soft error due to α-rays.
In other words, the storage capacitor has to retain a certain amount of storage capacity even though its area decreases in proportion to miniaturization. This object has been achieved by several contrivances.
They include making the capacitor insulating film thicker and forming the capacitor insulating film from a material with a high dielectric constant, thereby increasing storage capacity.
On the other hand, contrivances have also been made in the structure of capacitor electrode. The memory capacitor, which consists of a memory node electrode (connected to a transistor), a plate electrode (connected to earth), and a capacitor insulating film interposed between them, may be formed in stack type or trench type. In the former case, the components are stacked one over another. In the latter case, the memory node electrode extends in the depthwise direction of the semiconductor substrate. Both structures increase the opposing surface areas of the memory node electrode and the plate electrode, thereby increasing the storage capacity of the capacitor.
A description is given below of the above-mentioned DRAM with trench-type capacitors.
FIG. 15A is a sectional view of a memory cell of a DRAM according to the first conventional embodiment. FIG. 15B is a plan view of the memory cell. The sectional view in FIG. 15A is taken along the line X–X′ in FIG. 15B.
There is shown a p-type semiconductor substrate 100. A trench TR is formed in the region excluding a first n-type semiconductor layer 101 which becomes the active region AA. A second n-type semiconductor layer 102 is formed in a prescribed depth from the inner wall of the trench TR. It functions as the plate electrode PL or the memory capacitor.
A capacitor insulating film 103 is formed which covers the inner wall of the trench TR. Its inside is filled with a third n-type semiconductor layer 104 of polysilicon, which functions as the memory node electrode MN of the memory capacitor.
As mentioned above, the memory capacitor is composed of a second n-type semiconductor layer 102 (plate electrode PL), a capacitor insulating film 103, and a third n-type semiconductor layer 104 (memory node electrode MN).
The first n-type semiconductor layer 101 (active region AA) is separated by an element isolation insulating film 105 of STI (Shallow Trench Isolation) type of silicon oxide, in which is buried a fourth semiconductor layer 106 of polysilicon.
In the first n-type semiconductor layer 101 (active region AA) are a channel forming region and a source-drain region (not shown) holding it. On the first n-type semiconductor layer 101 (active region AA) in the channel forming region is a gate electrode 107 which is formed with a gate insulating film (not shown) interposed thereunder.
The MOSFET constructed as mentioned above has one source-drain electrically connected to the third n-type semiconductor layer 104 (the memory node electrode MN of the memory capacitor) through the semiconductor layer 106 and another source-drain connected to a bit line (not shown) through the bit contact 108. It also has the gate electrode 107 connected to a word line. A large number of memory cells each constructed as mentioned above are put together into a matrix pattern to form a DRAM.
In the above-mentioned structure, the connection of the fourth semiconductor layer 106 to the source-drain region in the first n-type semiconductor layer 101 is accomplished by impurity diffusion from the fourth semiconductor layer 106 to the first n-type semiconductor layer 101.
This connecting method has restrictions on the trench area as follows.
(1) Connecting the fourth semiconductor layer 106 to the first n-type semiconductor layer 101 by impurity diffusion requires a certain distance between the end of the trench and the end of the gate electrode, which implies that the fourth semiconductor layer 106 should be sufficiently far away from the channel forming region in the first n-type semiconductor layer 101 so that the MOSFET fully exhibits its characteristic properties.
(2) A certain distance has to be secured from the active region AA of the adjoining cell for another bit.
Unfortunately, any attempt to remove the above-mentioned restrictions on the trench-type capacitor meets more difficulties in securing the sufficient trench diameter as miniaturization proceeds.
Consequently, it has become common practice to design the trench to be deeper than 5 μm in order to secure the surface area of the opposing planes of the memory node electrode and the plate electrode and to secure the storage capacity of the memory capacitor.
On the other hand, Patent Document 1 discloses a DRAM which has a trench-type capacitor (consisting of a memory node electrode, a capacitor insulating film, and a plate electrode) buried in the substrate and planarized and bonded to another silicon substrate through an insulating layer.
A description is given below of the above-mentioned DRAM with trench-type capacitors buried in the substrate.
FIG. 16A is a sectional view of a memory cell of a DRAM according to the second conventional embodiment. FIG. 16B is a plan view of the memory cell. The sectional view in FIG. 16A is taken along the line X–X′ in FIG. 16B.
There is shown a semiconductor substrate 10. There is also shown a trench TR which is partitioned by a trench wall 10a and a mask layer 11. The mask layer 11 is the layer which was used as a mask when the trench TR was formed.
There is shown a first n-type semiconductor layer 12 extending to a certain depth from the surface of the inner wall of the trench TR. It functions as the plate electrode PL of the memory capacitor.
There is shown a capacitor insulating film 13 which covers the surface of the inner wall of the trench TR. A second n-type semiconductor layer 14 of polysilicon is buried inside the capacitor insulating film 13. It functions as the memory node electrode MN of the memory capacitor.
As mentioned above, the memory capacitor is composed of a first n-type semiconductor layer 12 (plate electrode PL), a capacitor insulating film 13, and a second n-type semiconductor layer 14 (memory node electrode MN).
The above-mentioned memory capacitor is covered sequentially with an interlayer insulating film 15 of silicon oxide and a third n-type semiconductor layer 16 of crystalline silicon (which functions as the active region AA).
The third n-type semiconductor layer 16 (active region AA) is separated by an element isolation insulating film 105 of STI type of silicon oxide.
There is shown a fourth semiconductor layer 18 of polysilicon. It is buried in the contact hole which is formed in the boundary region between the element isolation insulating film 17 and the third n-type semiconductor layer 16 such that it reaches the second n-type semiconductor layer 14 (memory node electrode MN).
In the third n-type semiconductor layer 16 (active region AA) are a channel forming region and a source-drain region (not shown) holding it. On the third n-type semiconductor layer 16 (active region AA) in the channel forming region is a gate electrode 19 which is formed with a gate insulating film (not shown) interposed thereunder.
The MOSFET constructed as mentioned above has one source-drain electrically connected to the second n-type semiconductor layer 14 (the memory node electrode MN) through the fourth semiconductor layer 18 and another source-drain connected to a bit line (not shown) through the bit contact 20. It also has the gate electrode 19 connected to a word line.
A large number of memory cells each constructed as mentioned above are put together into a matrix pattern to form a DRAM.
The DRAM having memory cells as mentioned above is constructed such that the MOSFET and the memory capacitor are placed on top of the other, with the interlayer insulating film 15 interposed between them. This structure permits the area of the memory capacitor to be maximized without limitations by the active region AA. Thus there is no need for the trench to be deeper than necessary. In addition, the trench can be made to have a large opening, which facilitates the lithography process and greatly reduces the etching time.
The DRAM having the above-mentioned memory cells is produced by the following process.
First, the semiconductor substrate 10 has the trench TR formed therein which becomes the capacitor later. The trench TR has the first n-type semiconductor layer 12 (plate electrode PL) and the capacitor insulating film 13 formed sequentially on its internal wall surface. The trench TR is filled with polysilicon deposited therein. Subsequently, the polysilicon undergoes etch-back.
Silicon oxide is deposited to form the interlayer insulating film 15, which is subsequently covered with the third n-type semiconductor layer 16, in which is formed the element isolation insulating film 17 by STI method.
A contact hole reaching the second n-type semiconductor layer 14 (memory node electrode MN) is made, and then it is filled with polysilicon to form the fourth semiconductor layer 18, which connects the second n-type semiconductor layer 14 to the source-drain region of the transistor to be formed in the third n-type semiconductor layer 16.
On the third n-type semiconductor layer 16 are formed the gate electrode 19, the source-drain region, and the bit contact 20.
According to the process mentioned above, the fourth semiconductor layer 18 (memory node contact plug) to connect the second n-type semiconductor layer 14 (memory node electrode MN) to the source-drain region should be formed from polysilicon containing a conductive impurity before the gate electrode is formed. This impurity is diffused from the fourth semiconductor layer 18 into the third n-type semiconductor layer 16 by heat treatment to be performed later. The thus diffused impurity serves for connection to the region which becomes the source-drain region later.
In this case, the gate electrode should be a certain distance away from the end of the diffused layer, and this necessitates to provide a certain distance for alignment of lithography to make the contact hole opening with lithography to form the gate electrode.
[Patent Document 1]
Japanese Patent Laid-open No. Hei 6-104398